1. Field of the Invention
The invention relates to structures and methods of fabricating integrated CMOS circuits, and more particularly to making those CMOS circuits highly immune to latchup.
2. Description of the Related Art
Latchup is a phenomenon of CMOS circuits well known to circuit designers and is described by S. Wolf in Silicon Processing for the VLSI Era, Volume 2, by Lattice Press, copyright 1990, 6.4 LATCHUP IN CMOS. The inherent and self-destructive latchup effect in CMOS circuits which has always been a major problem has become even more so a problem as device dimension continue to shrink. The latchup phenomenon creates a low resistance path between the positive and negative voltage supplies of a CMOS circuit and enables the flow of large currents through the affected circuit. When latchup occurs the circuit stops functioning and may even get destroyed because of the heat developed by the large currents.
Latchup is caused by the presence of parasitic bipolar pnp and npn transistors in the structure of PMOS and NMOS transistors. The closer those complementary MOS transistors are to each other the more there is a likelihood of those parasitic transistors to interact electrically to form a pnpn diode, equal to a silicon controlled rectifier (SCR). Internal voltages across the anode and cathode of that SCR which exceed a breakover voltage cause the SCR to reach a low impedance state with the possibility of a resultant high current. This state can be maintained indefinitely if an external circuit can supply a necessary holding current, i.e., the SCR stays latched up and the circuit cannot recover.
FIG. 1 shows a cross-sectional view of a prior art CMOS device layout 100. Embedded in a p-substrate 102 is an n-well 104 containing a plurality of p+ regions 106 which are both source and drain. An n+ guard-ring 108 located at the perimeter of the n-well surrounds regions 106. Similarly, a plurality of n+ regions 116, of both source and drain, are formed in the p-substrate 102 and are surrounded by a p+ guard-ring 118. Gates 109 and 119 are indicated straddling sources and drains of regions 106 and 116, respectively. The parasitic SCR inherent in CMOS structures is comprised of transistor Q1 and Q2. Q1 is a vertical bipolar pnp parasitic transistor structure and Q2 is a lateral bipolar npn parasitic transistor structure resulting from the arrangement of the PMOS transistors of regions 106 and of the NMOS transistor of regions 116. The emitter of Q1 comprises the sources of regions 106, the base comprises n-well 104 and the collector comprises p-substrate 102. Analogous the emitter of Q2 comprises the sources of regions 116, the base comprises p-substrate 102 and the collector comprises n-well 104. Between guard-ring 108 and the base of Q1 is the bulk n-well resistance 130. Between guard-ring 118 and the base of Q2 is the bulk p-substrate resistance 132. Bulk resistances 130 and 132 each have a value of about 100 Ohms.
FIG. 2 is an equivalent circuit diagram of the parasitic transistors of FIG. 1 and represents the above mentioned pnpn diode or SCR. One terminal of resistor 130 (equal to guard-ring 108) and the emitter of Q1 (equal to the source of region 108) is connected to a positive voltage Vcc. One terminal of resistor 132 (equal to guard-ring 118) and the emitter of Q2 (equal to the source of region 116) is connected to a negative voltage Vss, typically ground.
The above described arrangement for I/O devices with guard ring structures is latchup free as long as NMOS and PMOS transistors are 15 micron or more apart. At distances below 15 micron these structures start exhibiting latchup. Another way to avoid latchup is to use EPI wafers to reduce the resistivity of the substrate resistor with a resultant higher cost.
Attempts by device designers to overcome the latchup problem are legions and of a great variety, each providing solutions applicable to the then current technological restraints and requirements. As circuit dimensions continue to shrink new device structures become necessary. The inventions described subsequently address and solve the latchup problem.
The following three U.S. Patents may be considered relating to the present invention:
U.S. Pat. No. 5,023,689 (Sugawara) illustrates a complementary integrated circuit device having a guard ring region surrounding a region having transistors that are larger than those in a second region do. The guard ring region is supplied with a power voltage via a conductor line, which is formed separately from a conductor line supplying the power voltage to each of the larger transistors.
U.S. Pat. No. 5,406,513 (Canaris et al.) shows a CMOS circuit formed in a semiconductor substrate having improved immunity to radiation induced latch-up and improved immunity to a single event upset. A continuous P+ guard ring is formed surrounding the n-channel transistors and between the n-channel transistors and an N-Well. Similarly, a continuous N+guard ring is formed surrounding the p-channel transistors and between a p-channel transistors and the p-type substrate. In the event of a radiation hit, the guard rings operate to reduce the parasitic impedance in the collector circuits of the parasitic bipolar transistors forming a parasitic SCR and also act as additional collectors of radiation induced current.
U.S. Pat. No. 5,895,940 (Kim) describes integrated circuits having built-in electrostatic discharge protection thyristors. Guard rings are formed in a first well region and a second well region to complete the structures of a pair of thyristors. The guard rings are preferably electrically connected to reference potentials so that damage caused by excessive voltage can be inhibited upon latch-up of the built-in thyristors.
It should be noted that none of the above-cited examples of the related art reduce sufficiently the n-well or p-substrate resistance at decreased circuit dimensions or reduced NMOS-to-PMOS spacings to avoid latchup.
It is an object of the present invention to provide new CMOS I/O structures and methods which improve their latchup immunity.
Another object of the present invention is to decrease the spacing between the NMOS and PMOS devices to 5 micron while maintaining improved latchup immunity.
These objects have been achieved in a first preferred embodiment by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring.
In a second preferred embodiment of the present invention a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs.
The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively. In either of the two preferred embodiments the shunt resistances are reduced to less than 3 Ohms, thereby preventing the forward biasing of the parasitic bipolar transistors of the SCR.